by aklofas
AI-powered Claude Code skills for KiCad electronics design. Analyze schematics, review PCB layouts, download datasheets, source components, and prep boards for fabrication
# Add to your Claude Code skills
git clone https://github.com/aklofas/kicad-happyClaude Code skills for electronics design with KiCad. Analyze schematics, review PCB layouts, download datasheets, source components, and prepare boards for fabrication β all from your terminal.
π οΈ Requires Claude Code β Anthropic's agentic coding tool that lives in your terminal. Skills like these let you extend it into entirely new domains beyond software.
These skills turn Claude Code into a full-fledged electronics design assistant that understands your KiCad projects at a deep level: parses schematics and PCB layouts into structured data, cross-references component values against datasheets, detects common design errors, and walks you through the full prototype-to-production workflow.
| Skill | What it does | | ------------- | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | | kicad | β‘ Parse and analyze KiCad schematics, PCB layouts, Gerbers, and PDF reference designs. Automated subcircuit detection, design review, DRC/ERC verification. | | bom | π Full BOM lifecycle β analyze, source, price, export tracking CSVs, generate per-supplier order files. | | digikey | π Search DigiKey for components and download datasheets via API. | | mouser | π Search Mouser for components and download datasheets. | | lcsc | π Search LCSC for components (production sourcing, JLCPCB parts library). | | element14 | π Search Newark/Farnell/element14 for components (international sourcing, one API for three storefronts). | | jlcpcb | π JLCPCB fabrication and assembly β design rules, BOM/CPL format, ordering workflow. | | pcbway | π PCBWay fabrication and assembly β turnkey assembly with MPN-based sourcing. |
The easiest way β just ask Claude Code:
Clone https://github.com/aklofas/kicad-happy and install all the skills
And keep up to date with the latest as we use our test harness to validate against a corpus of open source projects.
Claude, pull the latest changes for kicad-happy and update my skills
Or do it manually:
git clone https://github.com/aklofas/kicad-happy.git
cd kicad-happy
# Install all skills (symlinks into ~/.claude/skills/)
mkdir -p ~/.claude/skills
for skill in kicad bom digikey mouser lcsc element14 jlcpcb pcbway; do
ln -sf "$(pwd)/skills/$skill" ~/.claude/skills/$skill
done
You can also install individually β symlink any skill folder from skills/ into ~/.claude/skills/. For project-specific installs, use .claude/skills/ in your project root instead.
The kicad skill is the core β the others enhance it with sourcing, datasheets, and manufacturing workflows.
The analysis scripts are pure Python 3 with no required dependencies. Optional extras:
requests β better datasheet downloads (handles HTTP/2, manufacturer anti-bot)playwright β last-resort fallback for JS-heavy datasheet sites (Broadcom, Espressif)pdftotext (poppler-utils) β better PDF text extraction for datasheet verificationThe distributor skills work best with API credentials, but none are strictly required β Claude falls back to web search for component lookups and datasheet downloads.
"Claude, help me set up API keys for the distributor skills"
| Distributor | Env variables | How to get |
| ------------- | -------------------------------------------- | ------------------------------------------------------------------------------------------------------ |
| DigiKey | DIGIKEY_CLIENT_ID, DIGIKEY_CLIENT_SECRET | DigiKey API Portal β register an app, get OAuth 2.0 credentials |
| Mouser | MOUSER_SEARCH_API_KEY | My Mouser β APIs β register for Search API key |
| element14 | ELEMENT14_API_KEY | element14 API Portal β one key covers Newark, Farnell, and element14 |
| LCSC | none needed | Uses the free jlcsearch community API |
"Analyze my KiCad project at
hardware/rev2/"
Claude runs the analysis scripts, reads datasheets, and produces a full design review. Here's a condensed example from a real project β a 6-layer BLDC motor controller (187 components):
Power tree β every regulator traced from input to output, feedback dividers identified, output voltage computed:
V+ (10-54V motor bus, TVS protected)
βββ MAX17760 buck β +12V (feedback: 226k/16.2k, Vref=1.0V β Vout=14.95V)
β βββ TPS629203 β +5V β TPS629203 β +3.3V
βββ DRV8353 gate driver (PVDD = V+ direct)
βββ 3-Phase Bridge: 6x FDMT80080DC (80V/80A)
βββ 36x 4.7uF 100V bulk caps = 169.2uF
Detected subcircuits β found automatically from the schematic:
| Subcircuit | Details | | ----------- | -------------------------------------------------------------------------------------------------- | | Motor drive | 6 FETs, gate driver, per-phase current sense (0.5mΞ©), 3x matched RC filters (22Ξ© + 1nF = 7.23 MHz) | | Buses | 2x SPI, CAN with 120Ξ© termination, RS-422 differential | | Protection | TVS on V+ input (51V standoff matches bus spec), ground domain separation with net ties | | Sensing | Battery voltage divider (100k/4.7k β 54V max reads as 2.43V), FET temp NTC |
PCB cross-reference β the review covers layout too:
Board: 56.0 x 56.0 mm, 6-layer, 1.55mm stackup
Routing: 100% complete, 0 unrouted nets
Thermal pad vias:
Phase FETs: 21-85 vias per pad β good
STM32 QFN-48: 14 vias β WARNING (recommended: 16)
Inductor L2: 4 vias β INSUFFICIENT (recommended: 9)
Issues found:
| Severity | Issue | | ---------- | -------------------------------------------------------------------------------------------- | | WARNING | Feedback divider computes to 14.95V, not 12V β Vref heuristic may be wrong, verify datasheet | | WARNING | STM32 thermal pad has 14 vias (need 16) β elevated die temp under load | | WARNING | Inductor L2 has 4 thermal vias (need 9) β carries the full +12V rail current | | SUGGESTION | No test point on V+ motor bus β add for bring-up measurements |
What looks good: 170Β΅F bus capacitance across 38 caps, proper GND/GNDPWR domain separation, CAN bus termination verified, 100% MPN coverage across all components, zero DFM violations, JLCPCB standard tier compatible.
For a complete example, see the full design review of an ESP32-S3 board β 52 components, 2-layer, dual boost converters, USB host, touch sensing.
The analysis covers every domain in the design:
| Category | Examples | | ----------------- | -------------------------------------------------------------------------------------------------- | | Power | Regulator Vout computed from feedback dividers, power sequencing, enable chains, inrush analysis | | Analog | Op-amp gain computation, voltage dividers with ratios, RC/LC filter cutoff frequencies | | Protection | TVS/ESD mapping per interface, MOSFET switch gate drive analysis, flyback diode checks | | Digital | I2C pull-up verification, SPI/UART/CAN bus detection, differential pairs, level crossing analysis | | Motor/Power | H-bridge and 3-phase bridge detection, current sense shunts, gate driver mapping | | RF | Signal chains, switch matrices, mixer/LNA/PA identification, balun detection | | PCB | Thermal via adequacy, zone stitching density, trace width vs current, DFM checks, tombstoning risk | | Manufacturing | BOM consolidation opportunities, MPN coverage audit, assembly complexity scoring |
The analysis scripts parse KiCad's S-expression file format directly into structured JSON β component lists, net connectivity, detected subcircuits, board dimensions, DFM measurements. Claude then reads that JSON alongside your datasheets to cross-reference values, trace signal paths, and write a design review with every conclusion shown and verifiable. For the full end-to-end walkthrough from S-expression parsing through signal detection, datasheet cross-referencing, design review, and discussion of limitations β see How It Works. Det
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